Computer Architecture: A Quantitative Approach – Hennessey & Patterson (5thedition)

 Course Objectives:

How instructions are executed at a very low level, and, with a high degree of detail.

Techniques to increase instruction execution performance will be covered throughout the semester; quantitatively analyzing each new strategy will also be covered.

Pipelining, multi-level cache memory, and branch prediction will be emphasized.

Vector processing, VLIW, EPIC and other parallel processing designs will be investigated.

idterm exam, (M) 3/5/18 (Chapter. 1, Appendices A, C

and parts of J)           30% (Mid to late PM)

    Final exam – (S)  5/7/14, (9AM-Noon)                                       30%

    Quizzes and homework                                                              20%

    Research paper and two other related assignments              20%

            (2% for 15-20 minute presentation on 4/27 (F), or 4/28(Sat): SMC Symp.)


Prof. John A. Trono, JeanMarie 267, x2432

Office Hours are: MW 1:30-3:30pm, T & TH 3-4pm, or by appt.

It is expected that you will need to spend, on average, at least 8 hours per week, in addition to your attendance in my lectures, to be able to; read the designated portions of the textbook; complete all homework assignments; research and write your research paper (and create your accompanying public presentation) as well as studying for quizzes and exams.


 (#Lectures M-W-F, 40 in all, which does not include midterm exam and review before the final)


(2)     Read the Forward, Preface, and Chapter 1 (skimming 1.5-1.7)

          - Introduction to computer architecture.

- Introducing the M0 (“em zero”) machine architecture

 (4)    Appendix A

          - Measuring a machine’s performance

          - Instruction set design and principles

- RISC vs. CISC architectures

- Hardware and micro-programmed control of M0   

 (2)   Appendix pages J2 to J-13, J-37 to J-50, J-13 to J-17

- Data representation; mostly integers and floating point (but some others data types)

          - How addition is performed on these representations.

(1)     - External bus operations and strategies

(5)     Sections of Chapter 2.3

- Primary memory design as well as memory interleaving hardware.

(8)    - The MIPS Architecture (Appendix pages C-2 to C-70)

- A hardware control unit for MIPS.

          - Pipelined CPU micro-architecture (then the midterm)

(3)  Appendix B.1 through B.3, and chapter sections 2.1 & 2.2.

- Data (and instruction) caches.

(7)     - Advanced pipelining and Instruction Level Parallelism (ILP). C-70 to the end, Chpt. 3

          - PowerPC, DEC Alpha, and Intel Pentium IV implementations

(3)     - Powerful SIMD/Vector machines - Appendix G.1-G.4, G.7 & G.8 and Chapter 4

(6)     - Parallel architectures (ILLIAC IV, CM*, etc.) – Some sections in Chap 5 - and - H.6

- Interconnection Networks (F-29 to F-37)

          - Data flow architectures (Manchester, UK: actual dataflow machine)

- Advances in computer architecture: VLIW and EPIC (Intel Itanium in H.6).

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