Computer Architecture: A Quantitative Approach
(Hennessey & Patterson - 4^th edition)

    Midterm exam, (F) 2/27/09 (Chapters 1, Appendices A, B and
                                                                             parts of I, J & K)    30%

    Final exam, (WT) 5/6/09, 1-4pm                                                  30%

    Quizzes and homework                                                                 20%

    Research paper and five shorter writing assignments              20%

(#Lectures M-W-F, 40 in all, which does not include midterm exam and review before the final)
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(2) Read the Forward, Preface, and Chapter 1 (skim 1.4-1.7), K.1 & K.2
            - Definitions and taxonomy of computers and their underlying architectures.
            -The Von Neumann architecture
            - Introducing the M0 (“em zero”) machine architecture

(4) Appendix B, two portions about the 80x86: J-45 to J-50, J-55 to J-57, and J-65 to J-72 (VAX)
            - Measuring a machine’s performance
            - Instruction set design and principles
            - RISC vs. CISC architectures
            - Hardware and micro-programmed control of M0   

(4) Appendix pages I-2 to I-13, I-37 to I-50, I-13 to I-26
            - Data representation; mostly integers and floating point (but some others data types)
            - How arithmetic operations are performed on these representations.

(8)       - The MIPS Architecture (Appendix pages A-2 to A-66)
            - A hardware control unit for MIPS.
            - Pipelined CPU micro-architecture (then the midterm)

(1)       - External bus operations and strategies - Section 7.3

(5) Appendix C, early sections of Chapter 5
            -Primary memory design; interleaving, high speed caches and virtual memory.

(7)       - Advanced pipelining and Instruction Level Parallelism (ILP) – A-66 to the end, Chapter 3
            - PowerPC, Dec Alpha, and Intel Pentium IV implementations

(3)       - Powerful SIMD/Vector machines - Appendix F.1-F.4, & F.7-F.8

(6)       - Parallel architectures (ILLIAC IV, CM*, etc.) – Chapter 4, G.6, and H.7 & H.8
            - Interconnection Networks
            - Data flow architectures (Manchester, UK dataflow machine)
            - Advances in computer architecture: VLIW and EPIC (Intel Itanium), software
              morphing (Transmeta chip), etc. Early sections of Chapter 4 and 4.7

                                                                                                Prof. John A. Trono
                                                                                                JeanMarie 267, x2432
                                                                                                MW 2-3:30pm, T/Th 9:30-10:30am or by appt.
                                                                                               

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