CS313 - INTRODUCTION TO COMPUTER ARCHITECTURE
Computer Architecture: A Quantitative Approach – Hennessey & Patterson (5thedition)
How instructions are executed at a very low level, and, with a high degree of detail.
Techniques to increase instruction execution performance will be covered throughout the semester; quantitatively analyzing each new strategy will also be covered.
Pipelining, multi-level cache memory, and branch prediction will be emphasized.
Vector processing, VLIW, EPIC and
other parallel processing designs will be investigated. idterm exam, (M) 3/4/13 (Chapter. 1, Appendices A, C
idterm exam, (M) 3/4/13 (Chapter. 1, Appendices A, C
and parts of J) 30% (Mid to late PM)
Final exam – (F) 5/3/13, (9AM-Noon) 30%
Quizzes and homework 20%
Research paper and two other related assignments 20%
(2% for one short paper, and 2% for 10-12 minute presentation on Friday 4/20: SMC Symp.)
Prof. John A. Trono, JeanMarie 267, x2432
Office Hours are: MW 3-4pm, T 9-10:30am, or by appt.
(2) Read the Forward, Preface, and Chapter 1 (skimming 1.5-1.7)
- Introduction to computer architecture.
- Introducing the M0 (“em zero”) machine architecture
- Measuring a machine’s performance
- Instruction set design and principles
- RISC vs. CISC architectures
- Hardware and micro-programmed control of M0
- Data representation; mostly integers and floating point (but some others data types)
- How arithmetic operations are performed on these representations.
- A hardware control unit for MIPS.
- Pipelined CPU micro-architecture (then the midterm)
(1) - External bus operations and strategies
(5) Appendix B.1 through B.3, sections of Chapter 2 (as announced in class)
- Primary memory design; interleaving, high speed caches and virtual memory.
(7) - Advanced pipelining and Instruction Level Parallelism (ILP). C-70 to the end, Chpt. 3
- PowerPC, DEC Alpha, and Intel Pentium IV implementations
(3) - Powerful SIMD/Vector machines - Appendix G.1-G.4, G.7 & G.8 and Chapter 4
(6) - Parallel architectures (ILLIAC IV, CM*, etc.) – Some sections in Chap 5 - and - H.6
- Interconnection Networks (F-29 to F-37)
- Data flow architectures (Manchester, UK: actual dataflow machine)
- Advances in computer architecture: VLIW and EPIC (Intel Itanium in H.6).
Back to Prof. Trono's Home page. (This page last modified January 08, 2003 .)